1. Field of the Invention
The present invention relates to a process for manufacturing an interlayer insulating film, and a display apparatus using this film and its manufacturing method.
2. Related Background Art
An SOG (Spin On Glass) film is conventionally generally used to flatten an interlayer insulating film, and this method is very effective in reducing the difference in the level of patterns (improving step coverage).
FIG. 10 is a sectional view of an interlayer insulating film in a semiconductor apparatus using the conventional technique.
In this figure, 1 is a semiconductor substrate, 2 is an insulating oxide film, 3 is a polycrystal silicon, 4 is an insulating film, 5 is a metal wiring, 6 is a first interlayer insulating film, 7 is an SOG film, 10 is a second interlayer insulating film, and 11 is a step inside a contact hole.
A conventional method is described below with reference to FIG. 10.
The insulating oxide film 2 is formed on the semiconductor substrate 1 using the selective oxidation process. Then, the polycrystal silicon 3 is deposited using the LP-CVD process, and the substrate is subjected to impurity-doping heat treatment and patterned using a photolithography step. In this manner, a semiconductor element is formed on the semiconductor substrate 1. The insulating film 4 is subsequently formed.
Then, patterning is executed to form a contact hole in the insulating film 4 for electric connections to the polycrystal silicon 3, a metal film is deposited thereon using the sputtering process, and the metal wiring 5 is formed thereon by patterning. Then, the P-CVD process is used to deposit the first interlayer insulating film 6. Then, the SOG film 7 is coated using the rotational coating process and is thermally treated. The etch back process is used to remove the flat part of the SOG film except for the periphery of the hole. Subsequently, the second interlayer insulating film 10 is deposited. After the interlayer insulating film of a multilayer structure is configured in this manner, a second metal wiring is formed.
The SOG film used to improve the flatness of the interlayer insulating film in the conventional example, however, often contains phosphorus to provide fluidity around the hole in the pattern. Thus, when the second metal wiring is formed in the subsequent process, the metal wirings may be corroded if the SOG is present around a hole called a "through-hole" that enables conduction between the first and second metal wirings. Consequently, the etching back process is required to remove the SOG only from this periphery. In addition, if an attempt is made to coat the SOG thick to reduce a step in a concave, the stress of the SOG may serve to produce a void to significantly degrade the electric characteristics of the element.
An organic SOG can be coated thick, but the CH.sub.3 radical of the organic SOG is transformed into a polymer during the formation of a through-hole to cause inappropriate conduction or to produce a void. Thus, the etch back process is also required in this case, and the interlayer insulating film may not be flattened.
Furthermore, in the interlayer insulating film formation process according to this conventional example, the SOG film is present only around the step, so a step occurs inside the contact hole (11 in FIG. 10) and a step in a concave can be reduced only in part of the surface of the interlayer insulating film, thereby preventing flattening. As a result, during the subsequent formation of a multilayer metal wiring, an open circuit may occur in the metal wiring due to the effect of a step in a concave inside the contact hole 11, thereby substantially reducing the reliability and yield of a display apparatus or a semiconductor device.
In addition, the flatness of the conventional interlayer insulating film in a semiconductor element used for a liquid crystal display apparatus is relatively insufficient.
FIG. 11 shows a sectional structure of an interlayer insulating film in such an example.
In this figure, 1 is a semiconductor substrate, 2 is a LOCOS insulating film, 3 is a gate electrode, 4 is a BPSG film, 5 is a metal electrode wiring, 6 is a first interlayer insulating film, 7 is an SOG, 8 is a second interlayer insulating film, 9 is a concave, 10 is a step.
According to a conventional general process for MOS transistors, a well region is formed in the semiconductor substrate 1, and an SiN film is deposited. Part of the SiN film is removed by patterning, and the LOCOS insulating film 2 is formed using the thermal oxidation process. Then, a gate oxide film and a thermally oxidized film are formed using the thermal oxidation process, and Poly-Si is deposited using the LP-CVD process. Impurities are introduced to reduce the resistance of the Poly-Si, and the photolithography process is used to execute patterning and etching to form the gate electrode 3. Subsequently, concentrated impurities are introduced into the well region using the self-alignment process and ion injection process, and heat treatment is applied to form a source and a drain regions. Then, an insulating film is deposited using the CVD process, and heat treatment is applied for reflowing. Then, the photolithography process is used to execute patterning and etching processing in order to form a contact hole, a metal film is deposited using the PVD process, and patterning and etching processing is executed again to form the metal electrode wiring 5. Subsequently, the first interlayer insulating film 6 is deposited using various CVD processes, the SOG film 7 is coated thereon using the rotational coating process, and after heat treatment, the second interlayer insulating film 8 using various CVD processes. Subsequently, a through-hole is formed, a metal film constituting a multilayer wiring and a reflector is deposited, and patterning and etching processing is repeated to form the multilayer wiring and reflector.
This interlayer insulating film formation process, however, uses an SOG film containing phosphorous for flattening, thereby requiring the etch back process for preventing the metal wiring from being corroded. The etch back process removes the SOG from the part contacted by the metal wiring to prevent corrosion, but it also reduces the capability of covering a step in a concave and the flatness of the interlayer insulating film, causing an open circuit in the multilayer metal wiring.
In addition, the high internal stress of the SOG film prevents its thickness from being increased. An organic SOG film can be used to compensate for this disadvantage, but also requires the etch back process due to its organic components. Thus, this film is also insufficiently reliable in terms of the metal wiring.
The stress of the phosphorous-containing SOG prevents its thickness from being increased, but the size of an SOG trap increases with decreasing length between the metal wirings. Particularly if the metal wiring is long and the length between the wirings is small, cracks often occur to increase leakage between the metal wirings or to reduce the yield.